Added problem set 3

main.tex

@@ -113,4 +113,145 @@ Full instructions can be found \href{https://docs.google.com/document/d/1e3DLurn
   \end{aligned}
 \]
 
+\newpage
+
+\section{Processor Organization, Datapath and Control Pathways}
+
+This homework consists of 4 questions (below), each of which is a multi-part answer. Full instructions can be found \href{https://docs.google.com/document/d/1c29Nl69fkJKi0PMUAC3jMjA8xqRfMCOTJm9KvJTGa7c/edit}{here}.
+
+\subsection{Question 1}
+
+\begin{center}
+  \includegraphics[scale=0.20]{resources/Set3_Q1.png}
+\end{center}
+
+\begin{enumerate}
+  \item Why is the width of the ID/EX buffer 128 bits? What values does it hold? \smallskip
+
+    This buffer is 128 bits because it holds the 32-bit values of the two registers read during the ID stage, the 32-bit sign-extended immediate value, the 6-bit funct field, the 5-bit register destination number, and a 26-bit control field for a total of 128 bits. \lbrack {P\&H 292p2, 296p2} \rbrack
+
+  \item Why is the width of the EX/MEM buffer 97 bits? What values does it hold? \smallskip
+
+    This buffer is 97 bits because it contains the 32-bit ALU result, the 32-bit value of the second register read during the ID stage (needed for store instructions), the 5-bit register destination number, the 26-bit control field, and a 2-bit field indicating the branch outcome for a total of 97 bits. \lbrack {P\&H 292p3,4} \rbrack
+
+  \item Why is the width of the EX/MEM buffer 97 bits? What values does it hold? \smallskip
+
+    This buffer is 97 bits because it contains the 32-bit data read from memory or the ALU result, the 5-bit register destination number, and a 27-bit control field for a total of 64 bits. \lbrack {P\&H 296p2} \rbrack
+
+\end{enumerate}
+
+\subsection{Question 2}
+
+\begin{center}
+  \includegraphics[scale=0.20]{resources/Set3_Q2.png}
+\end{center}
+
+\begin{enumerate}
+  \item What are the values of the 9 control signals generated by the control in Fig 4.17 for this instruction? \smallskip
+
+    \begin{center}
+      \begin{tabular}{|c|c|}
+        \hline
+        RegDst & 1 \\
+        \hline
+        ALUSrc & 0 \\
+        \hline
+        MemtoReg & 0 \\
+        \hline
+        RegWrite & 1 \\
+        \hline
+        MemRead & 0 \\
+        \hline
+        MemWrite & 0 \\
+        \hline
+        Branch & 0 \\
+        \hline
+        ALUOp1 & 1 \\
+        \hline
+        ALUOp0 & 0 \\
+        \hline
+      \end{tabular}
+
+      \lbrack {P\&H 266} \rbrack
+
+    \end{center}
+  \item What resources (logic blocks) perform a useful function that contributes to the final answer for this instruction? \smallskip
+
+    Instruction memory, PC, Adder (PC + 4), Registers, ALU, ALU Control, Multiplexer. \lbrack {P\&H Fig. 4.1} \rbrack
+
+  \item Which resources (logic blocks) produce outputs, but their outputs are not used for this instruction? \smallskip
+
+    Sign-extend, Multiplexer, Data Memory, Shift left 2, Adder, Multiplexer. \lbrack {P\&H 254} \rbrack
+\end{enumerate}
+
+\subsection{Question 3}
+
+Assume the following instructions and time requirements for each resource stage associated with each instruction:
+
+\begin{center}
+  \includegraphics[scale=0.28]{resources/Set3_Q3.png}
+\end{center}
+
+\begin{enumerate}
+  \item What is the clock cycle time required for a non-pipelined implementation that will accommodate all the instructions shown in the figure? \smallskip
+
+    \begin{center}
+      \begin{tabular}{|c|c|}
+        \hline
+        lw & 800 ps \\
+        \hline
+        sw & 700 ps \\
+        \hline
+        R-Format & 600 ps \\
+        \hline
+        Branch & 500 ps \\
+        \hline
+      \end{tabular}
+
+      \lbrack {P\&H 275} \rbrack
+    \end{center}
+
+  \item What is the clock cycle time for a pipelined implementation that will accommodate all the instructions shown in the figure? \smallskip
+
+    \begin{center}
+      \begin{tabular}{|c|c|}
+        \hline
+        Data access & 200 ps \\
+        \hline
+        ALU operation & 200 ps \\
+        \hline
+        Register read & 100 ps \\
+        \hline
+        Register write & 100 ps \\
+        \hline
+        Instruction fetch & 200 ps \\
+        \hline
+      \end{tabular}
+
+      \lbrack {P\&H Fig. 4.26} \rbrack
+    \end{center}
+
+  \item What is the total latency of the LW instruction in a non-pipelined implementation? \smallskip
+
+    800 ps
+
+  \item What is the total latency of the LW instruction in a pipelined implementation? \smallskip
+
+    1000 ps
+
+\end{enumerate}
+
+\subsection{NERSC Account Data}
+
+\begin{enumerate}
+  \item On what date and time did you submit your NERSC account request? \smallskip
+
+    Sept. 19th
+
+  \item What was your requested NERSC username? \smallskip
+
+    uzylol
+
+\end{enumerate}
+
 \end{document}