258 lines
8.3 KiB
TeX
258 lines
8.3 KiB
TeX
\documentclass{article}
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\usepackage{amsmath}
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\usepackage{fancyhdr}
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\usepackage{lastpage}
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\usepackage{hyperref}
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\usepackage{graphicx}
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\pagestyle{fancy}
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\fancyhf{}
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\fancyhead[L]{Uzair Hamed Mohammed}
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\fancyhead[C]{\thepage\ / \pageref{LastPage}}
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\fancyhead[R]{CSC 656-01 Fall 2024}
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\begin{document}
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\section{Truth Tables and Boolean Equations}
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Derive a truth table and sum-of-products representation for a function:
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\begin{itemize}
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\item Inputs: consist of 3 values – A, B, C – that may be either True or False
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\item Output: a single value – X – that is True when two and only two adjacent inputs are true
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\end{itemize}
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Full instructions can be viewed in the \href{https://docs.google.com/document/d/1XpSKpgN0JamxbZtsq-ZivZxFwIlkMH-9futUYkL0g2E/edit}{problem set 1 document}.
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\subsection{Truth Table}
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\begin{center}
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\begin{tabular}{|c|c|c|c|}
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\hline
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A & B & C & X \\
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\hline
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0 & 0 & 0 & 0 \\
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0 & 0 & 1 & 0 \\
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0 & 1 & 0 & 0 \\
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0 & 1 & 1 & 1 \\
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1 & 0 & 0 & 0 \\
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1 & 0 & 1 & 0 \\
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1 & 1 & 0 & 1 \\
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1 & 1 & 1 & 0 \\
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\hline
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\end{tabular}
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\end{center}
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\subsection{Sum-of-Products Representation}
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\[
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X = (!A \&\& B \&\& C) || (A \&\& B \&\& !C)
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\]
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\newpage
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\section{Truth Tables and Boolean Equations 2}
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Derive a truth table and sum-of-products representation for the function describing the operation of the 4-channel multiplexor shown in P\&H Fig B.5.10 (below).
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Full instructions can be found \href{https://docs.google.com/document/d/1e3DLurnuYyMFrjvi_6Wir7A7KS7h3gS3DyRhnOQJYMw/edit}{here}.
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\begin{center}
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\includegraphics[scale=0.25]{resources/Set2.png}
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\end{center}
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\subsection{Truth Table}
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\begin{center}
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\begin{tabular}{|c|c|c|c|c|c|c|c|}
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\hline
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Ainvert & Binvert & Less & S0 & S1 & S2 & S3 & Result \\
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\hline
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F & F & F & F & F & F & F & F \\
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F & F & F & F & F & F & T & T \\
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F & F & F & F & F & T & F & F \\
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F & F & F & F & F & T & T & T \\
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F & F & F & F & T & F & F & F \\
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F & F & F & F & T & F & T & T \\
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F & F & F & F & T & T & F & F \\
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F & F & F & F & T & T & T & T \\
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F & F & F & T & F & F & F & F \\
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F & F & F & T & F & F & T & T \\
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F & F & F & T & F & T & F & F \\
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F & F & F & T & F & T & T & T \\
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F & F & F & T & T & F & F & F \\
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F & F & F & T & T & F & T & T \\
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F & F & F & T & T & T & F & F \\
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F & F & F & T & T & T & T & T \\
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\hline
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T & T & T & T & T & T & T & T \\
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\hline
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\end{tabular}
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\end{center}
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\subsection{Sum-of-Products Representation}
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\[
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\begin{aligned}
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\text{Result} = & (!Ainvert \&\& !Binvert \&\& !Less \&\& !S0 \&\& !S1 \&\& !S2 \&\& S3) \\
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& \,|| (!Ainvert \&\& !Binvert \&\& !Less \&\& !S0 \&\& !S1 \&\& S2 \&\& !S3) \\
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& \,|| (!Ainvert \&\& !Binvert \&\& !Less \&\& !S0 \&\& !S1 \&\& S2 \&\& S3) \\
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& \,|| (!Ainvert \&\& !Binvert \&\& !Less \&\& !S0 \&\& S1 \&\& !S2 \&\& !S3) \\
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& \,|| (!Ainvert \&\& !Binvert \&\& !Less \&\& !S0 \&\& S1 \&\& !S2 \&\& S3) \\
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& \,|| (!Ainvert \&\& !Binvert \&\& !Less \&\& !S0 \&\& S1 \&\& S2 \&\& !S3) \\
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& \,|| (!Ainvert \&\& !Binvert \&\& !Less \&\& !S0 \&\& S1 \&\& S2 \&\& S3) \\
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& \,|| (!Ainvert \&\& !Binvert \&\& !Less \&\& S0 \&\& !S1 \&\& !S2 \&\& !S3) \\
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& \,|| (!Ainvert \&\& !Binvert \&\& !Less \&\& S0 \&\& !S1 \&\& !S2 \&\& S3) \\
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& \,|| (!Ainvert \&\& !Binvert \&\& !Less \&\& S0 \&\& !S1 \&\& S2 \&\& !S3) \\
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& \,|| (!Ainvert \&\& !Binvert \&\& !Less \&\& S0 \&\& !S1 \&\& S2 \&\& S3) \\
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& \,|| (!Ainvert \&\& !Binvert \&\& !Less \&\& S0 \&\& S1 \&\& !S2 \&\& !S3) \\
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& \,|| (!Ainvert \&\& !Binvert \&\& !Less \&\& S0 \&\& S1 \&\& !S2 \&\& S3) \\
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& \,|| (!Ainvert \&\& !Binvert \&\& !Less \&\& S0 \&\& S1 \&\& S2 \&\& !S3) \\
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& \,|| (!Ainvert \&\& !Binvert \&\& !Less \&\& S0 \&\& S1 \&\& S2 \&\& S3) \\
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& \,|| \ldots \\
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& \,|| (Ainvert \&\& Binvert \&\& Less \&\& S0 \&\& S1 \&\& S2 \&\& S3)
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\end{aligned}
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\]
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\newpage
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\section{Processor Organization, Datapath and Control Pathways}
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This homework consists of 4 questions (below), each of which is a multi-part answer. Full instructions can be found \href{https://docs.google.com/document/d/1c29Nl69fkJKi0PMUAC3jMjA8xqRfMCOTJm9KvJTGa7c/edit}{here}.
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\subsection{Question 1}
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\begin{center}
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\includegraphics[scale=0.20]{resources/Set3_Q1.png}
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\end{center}
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\begin{enumerate}
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\item Why is the width of the ID/EX buffer 128 bits? What values does it hold? \smallskip
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This buffer is 128 bits because it holds the 32-bit values of the two registers read during the ID stage, the 32-bit sign-extended immediate value, the 6-bit funct field, the 5-bit register destination number, and a 26-bit control field for a total of 128 bits. \lbrack {P\&H 292p2, 296p2} \rbrack
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\item Why is the width of the EX/MEM buffer 97 bits? What values does it hold? \smallskip
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This buffer is 97 bits because it contains the 32-bit ALU result, the 32-bit value of the second register read during the ID stage (needed for store instructions), the 5-bit register destination number, the 26-bit control field, and a 2-bit field indicating the branch outcome for a total of 97 bits. \lbrack {P\&H 292p3,4} \rbrack
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\item Why is the width of the EX/MEM buffer 97 bits? What values does it hold? \smallskip
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This buffer is 97 bits because it contains the 32-bit data read from memory or the ALU result, the 5-bit register destination number, and a 27-bit control field for a total of 64 bits. \lbrack {P\&H 296p2} \rbrack
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\end{enumerate}
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\subsection{Question 2}
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\begin{center}
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\includegraphics[scale=0.20]{resources/Set3_Q2.png}
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\end{center}
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\begin{enumerate}
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\item What are the values of the 9 control signals generated by the control in Fig 4.17 for this instruction? \smallskip
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\begin{center}
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\begin{tabular}{|c|c|}
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\hline
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RegDst & 1 \\
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\hline
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ALUSrc & 0 \\
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\hline
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MemtoReg & 0 \\
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\hline
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RegWrite & 1 \\
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\hline
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MemRead & 0 \\
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\hline
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MemWrite & 0 \\
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\hline
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Branch & 0 \\
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\hline
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ALUOp1 & 1 \\
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\hline
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ALUOp0 & 0 \\
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\hline
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\end{tabular}
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\lbrack {P\&H 266} \rbrack
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\end{center}
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\item What resources (logic blocks) perform a useful function that contributes to the final answer for this instruction? \smallskip
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Instruction memory, PC, Adder (PC + 4), Registers, ALU, ALU Control, Multiplexer. \lbrack {P\&H Fig. 4.1} \rbrack
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\item Which resources (logic blocks) produce outputs, but their outputs are not used for this instruction? \smallskip
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Sign-extend, Multiplexer, Data Memory, Shift left 2, Adder, Multiplexer. \lbrack {P\&H 254} \rbrack
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\end{enumerate}
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\subsection{Question 3}
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Assume the following instructions and time requirements for each resource stage associated with each instruction:
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\begin{center}
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\includegraphics[scale=0.28]{resources/Set3_Q3.png}
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\end{center}
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\begin{enumerate}
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\item What is the clock cycle time required for a non-pipelined implementation that will accommodate all the instructions shown in the figure? \smallskip
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\begin{center}
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\begin{tabular}{|c|c|}
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\hline
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lw & 800 ps \\
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\hline
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sw & 700 ps \\
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\hline
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R-Format & 600 ps \\
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\hline
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Branch & 500 ps \\
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\hline
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\end{tabular}
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\lbrack {P\&H 275} \rbrack
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\end{center}
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\item What is the clock cycle time for a pipelined implementation that will accommodate all the instructions shown in the figure? \smallskip
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\begin{center}
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\begin{tabular}{|c|c|}
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\hline
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Data access & 200 ps \\
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\hline
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ALU operation & 200 ps \\
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\hline
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Register read & 100 ps \\
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\hline
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Register write & 100 ps \\
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\hline
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Instruction fetch & 200 ps \\
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\hline
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\end{tabular}
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\lbrack {P\&H Fig. 4.26} \rbrack
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\end{center}
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\item What is the total latency of the LW instruction in a non-pipelined implementation? \smallskip
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800 ps
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\item What is the total latency of the LW instruction in a pipelined implementation? \smallskip
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1000 ps
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\end{enumerate}
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\subsection{NERSC Account Data}
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\begin{enumerate}
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\item On what date and time did you submit your NERSC account request? \smallskip
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Sept. 19th
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\item What was your requested NERSC username? \smallskip
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uzylol
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\end{enumerate}
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\end{document}
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